PROGRAM SCHEDULE
ISSM 2012 Abstract (as of Sept21)
Monday, October 15
Mon, Oct 15 | Tue, Oct 16 | Interactive | Wed, Oct 17
| 8:00 | Registration |
| 9:30 |
Opening Remarks Tadahiro Ohmi, Vice Chairman of Organizing Committee of ISSM2012, Tohoku University |
| 9:50 |
Keynote Speech - Toshiba's Semiconductor and Storage Products Strategy and the Renovation of the Semiconductor Industry in Japan. Shozo Saito, Director, Representative Executive Officer, Corporate Senior Executive Vice President, Toshiba Corp. |
| 10:50 |
Keynote Speech - What did I explore in Half a Century of Research? Dr. Leo Esaki, Nobel Laureate in Physics / President, Yokohama College of Pharmacy/Chairman, The Science and Technology Promotion Foundation of Ibaraki |
| 11:50 | Lunch |
| 13:00 |
The 20th Anniversary Speech - ISSM - Accelerator from "Know-how" to "Science" Yasuo Mizokami, Japan General Manager, Molecular Imprints, Inc. |
| 13:40 |
Highlight Session Process Control Solution Invited Talk: The Realities of Virtual Metrology Prof. Costas J. Spanos, Andrew S. Grove Distinguished Professor, Electrical Engineering and Computer Sciences, University of California, Berkeley |
Room A : Highlight Session - Process Control Solution
| 14:40 |
PC-O-18: Local overlay measurement and characterization for pitch-split double patterning process using CD-SEM Shoji Hotta, Hitachi |
| 15:00 |
PC-O-4: Multi-parametric Virtual Metrology Model Building by Job-shop Data Fusion Using a Markov Chain Monte Carlo Method Kenji Tamaki, Hitachi |
| 15:20 |
PC-O-31: Copper CMP APC for 32nm & 22nm Nodes Using Integrated Metrology Lin (Larry) Yang, IBM |
| 15:40 | Author's interview & Break |
| 16:00 |
PC-O-54: Bayesian Networks for maintenance planning in ion implantation Ulrich Schöpka, Fraunhofer IISB |
| 16:20 |
PC-O-21: Prediction and Control of Transistor Threshold Voltage by Virtual Metrology (Virtual PCM) using Equipment data Tomoya Tanaka, Panasonic |
| 16:40 |
PC-O-41: A dynamic overlay sampling scheme for APC in high-mix fab Chen-Fu Chien, National Tsing Hua University |
| 17:00 | Author's interview & Break |
| 17:20 | Networking Session time |
| 17:40 ~ 19:30 |
Reception |
Room B : MS/ES Session
| 14:40 |
MS-O-34: Static Capacity Planning and Scheduling Considering Product-Mix and Complex Tool Requirements in 300mm Semiconductor FAB Youngkook Kim, Samsung |
| 15:00 |
MS-O-88: Observations of the semiconductor market and technology in the last 20 years Keiji Horioka, Applied Materials |
| 15:20 |
MC-O-62: Real-Time Transfer Control Method for Linear Tools Teruo Nakata, Hitachi |
| 15:40 | Author's interview & Break |
| 16:00 |
MC-O-75: Effective Bottleneck Centric Allocation and Sequencing of Wet-bench and Furnace Tool Groups Yu-Ting Kao, National Taiwan University |
| 16:20 |
ES-O-6: Zero Manufacturing Wastewater in ATM Chai, Cheap LIam, Intel |
| 16:40 | Author's interview & Break |
| 17:00 | Networking Session time |
| 17:40 ~ 19:30 |
Reception |
Tuesday, October 16
Mon, Oct 15 | Tue, Oct 16 | Interactive | Wed, Oct 17
| 8:00 | Registration |
| 9:00 |
Keynote Speech - Technologies and Business Strategies of IT Industry in the Future Yoon Woo Lee, Executive Advisor, Samsung Electronics Co., Ltd. |
| 10:00 |
Keynote Speech - Leading through the present, anticipating the future Shizuo Igarashi, General Manager, Manufacturing and Technology, Texas Instruments Japan Ltd. |
| 11:00 |
Keynote Speech - Evolution of Semiconductor Device Technologies and the Revolution needed in Manufacturing Dr. Raj Jammy, Vice President of Emerging Technologies, SEMATECH |
| 11:40 |
Invited Talk - 3D-Integrated Circuits Technologies-The History and Future- Morihiro Kada, Association of Super-Advanced Electronics Technologies(ASET) |
| 12:20 | Lunch |
| 13:20 |
Highlight Session Printed Electronics Invited Talk : All-printed organic transistors for large-area, flexible electronics Dr. Tsuyoshi Sekitani, Research Associate, Quantum Phase Electronics Center and Department of Applied Physics, School of Engineering, The University of Tokyo |
Room A : UC/PO session
| 14:20 |
UC-O-87: Manufacturing challenges of GaN-on-Si HEMTs in a 200 mm CMOS fab Denis Marcon, IMEC |
| 14:40 |
UC-O-46: Ultra-Fine Particle Removal using Gas Cluster Beam Technology Kensuke Inai, Tokyo Electron |
| 15:00 |
UC-O-85: Study of airborne nanoparticle in cleanroom Eri Uemura, Toshiba |
| 15:20 | Author's interview & Break |
| 15:40 |
PO-O-12: MEOL Process Optimization for Low Cost TSV Fabrication Ryohei Kitao, Renesas Electronics |
| 16:00 | Author's interview & Break |
| 16:40 | 3miniutes Summary presentation by Interactive Poster Speaker |
| 17:30 | Break |
| 17:40 | Poster Session |
Room B : DM/PC/PE Session
| 14:20 |
Highlight Session Printed Electronics Invited Talk: Conductive paste for Flexible electronic application Takayuki Ogawa, Harima Chemicals |
| 14:40 |
DM-O-90: Designer-Friendly Half-Node Strategy of Logic Technology Based on Precise Yield-Aware Management of Lithography Misalignment Satoshi Nakai, Fujitsu Semiconductor Ltd. (Fujitsu Microelectronics) |
| 15:00 |
PC-O-5: Advanced thermal budget monitoring technique for spike annealing. Nao Higuchi, Renesas Electronics |
| 15:20 | Author's interview & Break |
| 15:40 |
PC-O-81: Resist patterning error detection technology of macro inspection tool for periphery of NAND Flash Makoto Oote, Toshiba |
| 16:00 |
PE-O-68: Wafer Edge Region Cleaning by Wet Blasting Akira Shiraishi, Raytex |
| 16:20 | Author's interview & Break |
| 16:40 | 3miniutes Summary presentation by Interactive Poster Speaker |
| 17:30 | Break |
| 17:40 | Poster Session |
3-min Summary Presentation for Interactive Poster Session
Mon, Oct 15 | Tue, Oct 16 | Interactive | Wed, Oct 17
Room A
| 17:00 ~ 17:50 |
FD-P-47: Facility Design through the Virtual Fab Simulation Toshikatsu Masuda, Toshiba |
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MC-P-57: The Principle of Cycle Time Worsening in Semiconductor Logistics WATANABE Hiroe, Panasonic |
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MC-P-60: Novel dispatching rule for re-entrant flow control in Q-time constraints processes Akihiro KOBAYASHI, University of Tsukuba |
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MC-P-61: Optimal Control of Engineering Operations on Production Tools in Semiconductor Manufacturing Naoto TOYOSHIMA, University of Tsukuba |
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UC-P-24: Reduction of Bevel Particle Induced by Wafer Backside Chemical Cleaning Pierre Loisel, TSMC |
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YE-P-29: Applications of Electron Tomography for Semiconductor Failure Analysis and Reference Metrology Hugh L. Porter, SEMATECH |
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YE-P-45: Intelligent Classification of Complicated Wafer Bin Map Patterns Chia-Yu Hsu, Yuan Ze University |
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YE-P-63: Knowledge searching system for particle cause Hidefumi Matsui, Tokyo Electron |
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PE-P-23: A novel method of PECVD film uniformity improvement by nitrogen carrier gas implement TSE-EN CHANG, TSMC |
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PE-P-44: Plasma chamber corrosions by earthquake Tsuyoshi Moriya, Tokyo Electron |
Room B
| 17:00 ~ 17:50 |
PO-P-15: Particle reduction in etching equipment re-startup from quake Toshikazu Hanawa, Renesas Semiconductor Engineering |
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PE-P-7: Quick Recovery of damaged clean room from quake hits Fumihiko Matsuoka, Renesas Electronics |
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DM-P-49: Pattern variation analysis using vision system based on higher-order local auto-correlation Tetsuaki Matsunawa, Toshiba |
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PO-P-76: EUV Resist Material and Process Development at EIDEC Eishi Shiobara, EIDEC |
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PO-P-77: EUVL resist pattern formation: an in situ analysis using HS-AFM Julius Joseph Santillan, EIDEC |
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PO-P-80: New SiC Power Device and Module Developments Tristan Evans, ROHM Co.,LTD |
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PC-P-19: Detection of Micro Arc Discharge Using ESC Wafer Stage with Built-in AE Sensor Yuji Kasashima, National Institute of Advanced Industrial Science and Technology(AIST) |
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PC-P-36: Excursion Reduction and Prevention Methodology Cougar Cheng, UMC / Carles Chen, Xilinx |
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PC-P-48: Development and Evaluation of Engineering Information System for Semiconducor Wafer Manufacturing Naoki Kawamura, Renesas Electronics |
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PC-P-104: Integrated Metrology for Advanced Lithography Process Control Paul Luehrmann, ASML |
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PO-P-92: Nitrogen Profile Engineering for Scaling SiON Gate Dielectrics with Improved Interface Quality, Gate Leakage and NBTI Performance Shenglin Wang, GLOBALFOUNDRIES |
Wednesday, October 17
Mon, Oct 15 | Tue, Oct 16 | Interactive | Wed, Oct 17
| 8:30 | Registration |
| 9:30 |
Keynote Speech - Innovations on Advanced Sub-system Integration Douglas Chen-Hua Yu, Ph.D., Senior Director, Integrated Interconnect and Package Division, R&D, Taiwan Semiconductor Manufacturing Co., Ltd. |
| 10:30 |
Keynote Speech - European Vision and Achievements Towards Larger Diameter Wafers Prof. Dr. Lothar Pfitzner, Head of "Semiconductor Manufacturing Equipment and Manufacturing Methods" at Fraunhofer Institute of Integrated Systems and Device Technology, Erlangen, Germany |
| 11:30 | Lunch |
| 12:50 |
Invited Talk - Power Device: Recent progress of SiC power device Hiroaki Sumitani, Mitsubishi Electric |
| 13:30 |
Highlight Session BCP Invited Talk: On-site Earthquake Early Warning System for Semiconductor plant Kenichi Takamatsu, Managing director of Environmental Div, Oki Engineering |
Room A : Highlight Session - BCP / YE Session
| 14:30 |
MS-O-37: Quake resistance improvement of wafer Fab learned from Great East Japan Earthquake Hidehiko Kawaguchi, Renesas Electronics |
| 14:50 |
FD-O-17: Anti-seismic measures of polyvinyl chloride (PVC) duct and clean room system ceiling Akinori Kawasaki, Renesas Electronics |
| 15:10 |
ES-O-58: Seismic Anchorage for Wafer Process Tools Capable for Severe Earthquake Shoji Ishida, Renesas Electronics |
| 15:30 |
FD-O-33: Wafer Carrier Fall-Off Protection Implementation for Automated Stokers Michiyuki Shimizu, Renesas Electronics |
| 15:50 | Author's interview & Break |
| 16:10 |
YE-O-55: Yield Improvement by Identifying a Precursor NVD as the Root Cause of Electrochemical Induced Pitting Defects at Gate Oxide Patterning Jungtae Park, Samsung |
| 16:30 |
YE-O-79: STI Crater Defect reduction for Semiconductor Device Yield Improvement Liang Li, GLOBALFOUNDRIES |
| 16:50 |
YE-O-014: Modeling with FDC data for yield enhancement C. T. Lin, TSMC |
| 17:10 | Author's interview & Break |
Room B : PO Session
| 14:30 |
PO-O-27: Fluoride Contamination Induced NiSi2 Film Formation in a Gate NiSi Line Takuya Futase, PhD, Renesas Electronics |
| 14:50 |
PO-O-16: Quantification and solution of wafer sticking in pattern plating Shinsuke Kozumi, Renesas Electronics |
| 15:10 |
PO-O-74: Optimization of a 65nm Back Illuminated CMOS Image Sensor by Varying Implant Angle YU WEI MING, TSMC |
| 15:30 |
PO-O-59: Control of Trench CD's Variations in a Deep Trench RIE Takayuki Sakai, Toshiba |
| 15:50 | Author's interview & Break |
| 16:10 |
PO-O-40: A Method of Clarification for Process Window of Cu Barrier/Seed for Void-Free Cu-Lines Kazuyuki Omori, Renesas Electronics |
| 16:30 |
PO-O-9: New Approach for Contact Dry Etch Process Optimization Hiroyuki Yazawa, Renesas Electronics |
| 16:50 |
PO-O-8: Optimization of groove structure for Cu-CMP pad Shinichiro Kakita, Renesas Electronics |
| 17:10 |
PO-O-95: Effect of Cu CMP Pad Clean on Defectivity and Reliability Leong Lup San, GLOBALFOUNDRIES |
| 17:30 | Author's interview & Break |